Method for plating independent conductor circuit

ABSTRACT

In wiring circuit board having fine and isolated conductor circuit pattern, a metal deposit coat is formed at desired position on the isolated conductor circuit pattern without damaging conductor circuit of the pattern, as an object of the invention. An electrically conducting layer consisting of a material electrically conducting and peelable with one of heat, solvent and alkali is formed on the wiring circuit board so as to be at least in contact with the isolated conductor circuit pattern on which the deposit coat is to be formed, a peelable protect layer is formed to be superposed on the electrically conducting layer at least at other portions than the portion where the deposit coat is to be formed, a metal deposition is performed on the portion not coated with the protect layer by means of an electroplating with the electrically conducting layer used as a power supply layer, and the electrically conducting and protect layers left on the wiring circuit board are peeled off.

TECHNICAL BACKGROUND OF THE INVENTION

This invention relates to a process for forming a deposit layer on anisolated conductor circuit pattern of wiring circuit boards employed inthe field of electronic material.

DISCLOSURE OF PRIOR ART

In recent years, technology has rapidly progressed in dimensionalminimization of electronic equipment, however there still exists anincreased demand for a higher mounting density Additionally there isdemand for a process to form a fine isolated conductor circuit patternof a wiring circuit board and further a need for a method of forming adeposit coat layer on only a part of the fine isolated conductor circuitpattern.

In forming the bumps, it has been generally known that, for example,other portions than the desired bump forming portions are coated with aresist to the plating, thereafter an electroplating is performed, andthen the resist is peeled off to obtain the bumps.

In the case of forming the bumps in the wiring circuit board having thefine and isolated conductor pattern by means of the conventionalelectroplating process, however, it has been required to have a dummyconductor circuit pattern for a power supply to the bump formingportions, and there have been such defects that the necessary conductorcircuit pattern is subjected to a side etching to cause a risk of wirebreakage to arise upon etching-removal of the dummy conductor circuitpattern after the bump formation or, in an event where such metal as Snis used for forming the bumps, there is a risk that Sn itself isexcessively damaged upon etching off the dummy conductor circuitpattern.

DESCRIPTION OF THE INVENTION

present invention has been suggested to overcome the foregoing problems,and its object is to provide a process of plating on isolated conductorcircuit, which process being capable of forming a metal deposit coat atdesired positions on the isolated conductor circuit pattern withoutgiving to the necessary conductor circuit pattern any damage, in thewiring circuit board having the fine and isolated conductor circuitpattern.

In order to establish the foregoing object, the process of plating onthe isolated circuit in an optimum embodiment of the present inventionis a process of plating on the isolated conductor circuit pattern of thewiring circuit board through the electroplating, characterized incomprising the steps of forming on the wiring circuit board anelectrically conducting layer with a material electrically conductiveand peelable with any one of heat, solvent and alkali, so as to be atleast in contact with the isolated conductor circuit pattern requiringthe formation of the deposit coat, forming a protect layer such as apeelable plating resist layer at least at other portions than thoserequiring the formation of the deposit coat and to be superposed on theelectrically conducting layer, depositing a metal at the portions wherethe protect layer is not formed through an electroplating with theelectrically conducting layer used as a power supply layer, and peelingoff the electrically conducting layer and protect layer left on thewiring circuit board.

In this case, it is possible to form the deposit coat on the isolatedconductor circuit pattern through the electroplating while supplying thepower through the electrically conducting layer without employing theconventional dummy conductor circuit, and further the electricallyconducting layer can be peeled off by means of heat, solvent or alkali,without requiring any etching by means of such strong acid or the likeas required for the conventional dummy conductor, so that the requiredconductor circuit pattern can be prevented from being damaged, and thedesired deposit coat can be stably formed.

Other objects and advantages of the present invention shall be madeclear in the following description detailed with reference toembodiments shown in accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1(a) to 1(d) show in sectioned views respective steps of platingon the isolated circuit in an embodiment according to the presentinvention;

FIGS. 2(a) to 2(e) show in sectioned views respective steps in anotherembodiment of the present invention;

FIGS. 3(a) to 3(e) are sectioned views for explaining respective stepsin another embodiment of the present invention;

FIGS. 4(a) to 4(f) are sectioned views for explaining respective stepsin still another embodiment of the present invention;

FIGS. 5(a) to 5(d) show in plan views for explaining the steps in theembodiment of FIG. 4;

FIGS. 6(a) and 6(b) are plan views for explaining other steps in theembodiment of FIG. 4;

FIG. 7 is a sectioned view for explaining part of steps in anotherembodiment of the present invention;

FIG. 8 is a plan view for explaining part of the steps in the embodimentof FIG. 7;

FIGS. 9(a) to 9(f) are sectioned views for explaining steps in anotherembodiment of the present invention;

FIGS. 10(a) to 10(d) show in plan views the steps of the embodiment ofFIG. 9;

FIGS. 11(a) and 11(b) are plan views for explaining further steps in theembodiment of FIG. 9;

FIG. 12 is a sectioned view for explaining part of steps in stillanother embodiment of the present invention;

FIG. 13 is a plan view for explaining part of the steps in theembodiment of FIG. 12;

FIGS. 14(a) to 14(f) are sectioned views for explaining steps in stillanother embodiment of the present invention;

FIGS. 15(a) to 15(d) show in plan views the steps in the embodiment ofFIG. 14;

FIGS. 16(a) and 16(b) are plan views for explaining another step in theembodiment of FIG. 14;

FIG. 17 is a sectioned view for explaining part of steps in anotherembodiment of the present invention;

FIG. 18 is a plan view for explaining the part of the steps in theembodiment of FIG. 17;

FIGS. 19(a) to 19(f) are sectioned views for explaining steps in anotherembodiment of the present invention;

FIGS. 20(a) to 20(d) are plan views for explaining the steps in theembodiment of FIG. 19;

FIGS. 21(a) and 21(b) are plan views for explaining another step in theembodiment of FIG. 19;

FIG. 22 shows in a sectioned view for explaining part of steps inanother embodiment of the present invention;

FIG. 23 is a plan view for explaining the part of the steps in theembodiment of FIG. 22;

FIGS. 24(a) to 24(f) are sectioned views for explaining steps in anotherembodiment of the present invention; and

FIGS. 25(a) to 25(f) are sectioned views for explaining steps in anotherembodiment of the present invention.

BEST MODE FOR WORKING THE INVENTION

The optimum embodiments of the present invention shall now be describedin the followings as detailed with reference to schematic step diagramsshown in FIGS. 1-3. In the process of plating on an isolated conductorcircuit according to the present invention, an electrically conductinglayer 13 is first formed as shown in FIGS. 1(a), 2(a) and 3(a) on awiring circuit board 12 so that the layer 13 will be at least in contactwith an isolated conductor circuit pattern 11 on which a deposit coat isrequired to be formed.

For the wiring circuit board 12 to be employed here, there are plasticwiring boards of a glass epoxy or polyimide resin, inorganic wiringboard of alumina, aluminum nitride or glass, and semiconductor substrateof silicone or gallium arsenic, while the board employed may not belimited to any specific one. The isolated conductor circuit pattern 11formed on the wiring circuit board 12 is to function as a terminal partconnected to an IC chip, for example, and is provided in a plurality ofrows, and the electrically conducting layer 13 is to be formed so as tobe in contact with a plurality of isolated conductor circuit patterns11.

This electrically conducting layer 13 forms an electrically conductivelayer having an electric conductivity, and is formed with a materialwhich can be peeled off by means of heat, a solvent or an alkali. As thematerial for the electrically conducting layer 13 here, one whichconsists of, for example, a heat peeling type resin, solvent peelingtype resin or an alkali peeling type resin, and an electricallyconductive substance added thereto. While it is preferable to add to theelectrically conducting layer 13 an electrically conductive filler asthe conductive substance, this should not be limited specifically. Inorder to secure the electric conductivity of the electrically conductinglayer 13, a powder of such metal as copper, silver or the like shouldpreferably be added. An addition of carbon powder is also optimum inreducing costs for the material of the electrically conducting layer 13.

While the process for forming the electrically conducting layer 13 shallnot be specifically limited, it is preferable to utilize a screenprinting or the like process in an event where the material for formingthe electrically conducting layer 13 is in, for example, a state ofpaste, but is optimum to form the layer by means of a thermocompressionbonding or the like process when the material is one of filmy moldings.So long as the material of the electrically conducting layer 13 is notphotosensitive, the electrically conducting layer 13 should be formed,as shown in FIGS. 1(a) and 2(a), so as to be in contact with theisolated conductor circuit pattern 11 at least at a deposit coat formingposition 14 at which a deposit coat is to be formed and disposed belowthis deposit-coat forming position. When, on the other hand, thematerial for the electrically conducting layer 13 is photosensitive, theelectrically conducting layer 13 may be formed all over the wiringcircuit board 12 as shown in FIG. 3(a). Since the electricallyconducting layer 13 acts as a power supply layer in electroplating laterperformed, the layer 13 should preferably be formed over to end edges ofthe wiring circuit board 12 as far as possible, for promotion of thepower supply during the plating.

Next, a protect layer 15 is formed to be superposed on the electricallyconducting layer 13 on portions other than the deposit-coat formingposition 14. While the protect layer 15 employed here shall not belimited to any specific material, any one of materials available in themarket may properly be selected in accordance with properties ofelectroplating solution employed. In forming the protect layer 15 and solong as the material for the layer 15 is in the paste state and is notphotosensitive, the formation at portions other than the deposit-coatforming position 14 and as superposed on the electrically conductinglayer 13 is made possible by means of the screen-printing or the likeprocess (see FIG. 1(b)). When the protect layer 15 is of aphotosensitive material, the protect layer 15 is formed at portionsincluding the position 14 of forming the deposit coat 17 and assuperposed on the electrically conducting layer 13 (FIGS. 2(b) and3(b)), and thereafter the protect layer 15 at the deposit-coat formingposition 14 (including the electrically conducting layer 13 when thislayer 13 is also photosensitive) is removed as in FIGS. 2(c) and 3(c)under predetermined conditions through an exposure and development.

Next, the electroplating is performed with the electrically conductinglayer 13 used as a power supply layer, and a metal 16 is caused to bedeposited as in FIGS. 1(d), 2(d) and 3(d) on the isolated conductorcircuit pattern 11 at portions where the protect layer 15 is not formed.This deposit metal 16 may properly be selected from Au, Sn and the likein accordance with connection specification.

Then, the electrically conducting layer 13 and protect layer 15 left onthe wiring circuit board 12 are peeled off under the predeterminedconditions (by means of heat, solvent or alkali), and the desireddeposit coat 17 is formed by the deposit metal 16 thus exposed as inFIGS. 1(d), 2(e) and 3(e). In an event when the electrically conductinglayer 13 is peeled off, the deposit coat 17 may happen to be oxidizeddepending on existing conditions, and it is desirable that a reductionor the like treatment is properly performed with such neutral solvent asdimethylamine volan solution or the like, after the peeling.

The process of plating on the isolated conductor circuit according tothe present invention as shown in FIGS. 1 to 3 shall be furtherdescribed in detail with reference to certain experiments.

EXPERIMENT 1:

A ceramic wiring circuit board 12 having the isolated conductor circuitpattern 11 formed with nickel-coated copper was prepared, and a samplewas prepared in accordance with the steps of FIG. 1. First, anelectrically conductive paste was prepared by dispersing silverparticles in a heat-peeling type resin and kneading them, and theelectrically conducting layer 13 was formed on the above wiring circuitboard 12 with this paste by means of the screen printing process (atother portions than the deposit-coat forming position 14 and to contactthe isolated conductor circuit pattern 11). Then, an alkali-peeling typeplating resist available in the market (non-photosensitive) in the stateof paste was printed by means of the screen printing process at portionsother than the deposit-coat forming position 14 and to be superposed onthe electrically conducting layer 13, the printed resist was dried andthe protect layer 15 was formed.

An electroplating of tin was performed to a thickness of 10 μm with theelectrically conducting layer 13 utilized as a power supply layer, andmetallic tin was deposited at the portions not coated by the protectlayer 15. Then, using an aqueous solution of sodium hydroxide, theprotect layer 15 left on the wiring circuit board 12 was first removed,and thereafter the remaining electrically conducting layer 13 was peeledoff through the heat treatment performed at 180° C. for 10 minutes.During the above heat treatment, the deposit coat metal of tin wasoxidized to some extent, and the reduction treatment was performed withthe aqueous solution of dimethylamine volan (pH 7), whereby theformation of the deposit coat 17 of tin was completed.

Since in this Experiment no etching treatment with any acid and the likewas performed, it was possible to obtain the desired deposit coat 17without damaging to the isolated conductor circuit pattern 11.

EXPERIMENT 2:

Except for the use of copper particles as dispersed and kneaded with theresin as the material for the electrically conducting layer 13, the samesteps as in Experiment 1 were performed to form the deposit coat 17. Asa result, it was possible to obtain the desired deposit coat 17similarly to Experiment 1, without damaging the isolated conductorcircuit pattern 11.

EXPERIMENT 3:

A ceramic wiring circuit board 12 was prepared with the isolatedconductor circuit pattern 11 formed with nickel-coated copper, and asample was arranged in accordance with the steps of FIG. 2. First, theelectrically conductive paste of the heat-peeling type resin wasprepared with carbon particles dispersed and kneaded, and theelectrically conducting layer 13 was formed on the wiring circuit board12 by means of the screen printing process (at portions other than thedeposit-coat forming position 14 and in contact with the isolatedconductor circuit pattern 11). Next, an alkali-peeling type,photosensitive paste of plating resist available in the market wasprinted by means of the screen printing process at the portion includingthe deposit-coat forming position 14 and to be superposed on theelectrically conducting layer 13, the printed resist was dried and theprotect layer 15 was formed.

Then, through the exposure and development of the protect layer, blindbore holes of 50 μmφ were made at the deposit-coat forming position 14,and the metal tin was deposited inside the blind bore holes through anelectroplating of tin to the thickness of 10 μm performed with theelectrically conducting layer 13 utilized as the power supply layer.Then the protect layer 15 left on the wiring circuit board 12 was firstremoved by using the aqueous solution of sodium hydroxide, andthereafter the remaining electrically conducting layer 13 was peeled offthrough the heat treatment made at 180° C. for 10 minutes. Since thesurface of tin forming the deposit coat was slightly oxidized during theabove heat treatment, the reduction treatment was performed with theaqueous solution of dimethylamine volan (pH 7), and the formation of thedeposit coat 17 of tin was completed. Without employment of the etchingtreatment by means of any acid in the present Experiment, too, thedesired deposit coat 17 could be obtained without damaging the isolatedconductor circuit pattern 11.

EXPERIMENT 4:

A printed wiring circuit board 12 having the isolated conductor circuitpattern 11 formed with nickel-coated copper was prepared, and a samplewas arranged in accordance with the steps of FIG. 3. The electricallyconductive paste was first prepared by dispersing carbon particles in aresin having the photosensitivity and alkali-peeling type, and kneadingthem, and the electrically conducting layer 13 was formed all over thewiring circuit board 12 by means of the screen printing process. Next,the alkali peeling type, photosensitive plating resist available in themarket was printed all over the wiring circuit board 12 except end partsof the board by means of the screen printing process, and the protectlayer 15 was formed.

Next, by subjecting the protect layer 15 and electrically conductinglayer 13 simultaneously to the exposure and development, blind boreholes of 50 μmφ were formed at the position 14 for forming the depositcoat. Then the electroplating of tin was performed to the thickness of10 μm with the electrically conducting layer 13 utilized as the powersupply layer, and the metal tin was deposited within the blind boreholes. Then the protect layer 15 and electrically conducting layer 13left on the wiring circuit board 12 were simultaneously peeled off bymeans of the aqueous solution of sodium hydroxide, and the formation ofthe deposit coat 17 of tin was completed. Without employing the etchingtreatment with any acid in the present experiment, too, the desireddeposit coat 17 could be obtained without damaging the isolatedconductor circuit pattern 11. As the alkali-peeling type, photosensitiveelectrically conducting layer 13 was employed in the present experiment,the peeling step could be shortened as compared with Experiment 1.

EXPERIMENT 5:

A ceramic wiring circuit board 12 having the isolated conductor circuitpattern 11 formed with nickel-coated copper was prepared, and a samplewas arranged in accordance with the steps of FIG. 3. An electricallyconductive paste was first prepared by dispersing copper particles in aphotosensitive, solvent-peeling type resin and kneading them, and theelectrically conducting layer 13 was formed all over the wiring circuitboard 12 by means of the screen printing process. Then thesolvent-peeling type, photosensitive plating resist in the state ofpaste and available in the market was printed by the screen printingprocess all over the wiring circuit board 12 except both end portions,to have the protect layer 15 formed.

Next, by subjecting the protect layer 15 and electrically conductinglayer 13 simultaneously to the exposure and development, the blind boreholes of 50 μmφ were formed at the position for forming the depositcoat. Then an electroplating of gold was performed to a thickness of 10μm with the electrically conducting layer 13 utilized for the powersupply, and gold was deposited within the blind bore holes. Then theprotect layer 15 and the electrically conducting layer 13 left on thewiring circuit board 12 were simultaneously peeled off with MEKemployed, and the formation of gold deposit coat was completed. In theabsence of the etching treatment by means of any acid also in thepresent experiment, the desired deposit coat could be obtained withoutdamaging the isolated conductor circuit pattern 11. By the employment ofthe solvent-peeling type, photosensitive electrically conducting layer13 in the present experiment, the peeling step could be shortened incomparison with the step in Experiment 1.

In performing the electroplating as has been described, the platingthickness is required to be excellent in the uniformity and, accordingto another feature of the present invention, there is provided anarrangement for improving the uniformity in the thickness of the depositcoat.

Referring to FIGS. 4 and 5, the arrangement for unifying the depositcoat as in the above is shown, in which such wiring circuit board 22 asshown in FIGS. 4(a) and 5(b) and provided on top surface with isolatedconductor circuit pattern 21 and with a power supply terminal 32 formedas separated from the pattern 21. The power supply terminal 32 is partto be used as a terminal for connection with a power source for thepower supply at a later described step of electroplating, and shouldpreferably be formed for ready connection to the power source bydisposing the terminal 32 to an extreme end edge part as much aspossible.

For the material of the wiring circuit board 22, such plastic board as aboard to which glass cloth is adhered with an epoxy resin or ofpolyimide or the like films, such inorganic board as alumina, aluminumnitride or glass and semiconductor board of silicone, gallium arsenic orthe like may be employable, but needs not be specifically limited. Forthe material forming the isolated conductor circuit pattern 21 or thepower supply terminal 32, such metal as copper, nickel or the like maybe used in general.

Next, as shown in FIGS. 4(b) and 5(b), a first electrically insulatingprotect layer 33 is formed on the wiring circuit board 22, so as to coatthe whole surface of the isolated conductor circuit pattern 21, exceptportions 24 for forming the deposit coat and portions 31 for connectionto the power source, and to expand from the coated surface of thecircuit pattern 21 to the power supply terminal 32.

For the material for forming the first protect layer 33, while notspecifically limited, any one of dry films, resin pastes and the likegenerally available in the market may be employed so long as they areelectrically insulating and do not hinder the later performedelectroplating. Generally, in the case of the dry film, the film isthermocompression-bonded and hardened at predetermined portions asexposed to light, then other portions not exposed to light are removed,and the first protect layer 33 is formed, whereas, in the case of theresin paste, the paste is applied onto the board by means of the screenprinting process or the like, and is hardened to form the first protectlayer 33.

In an event where the portions 24 for forming the deposit coat on theisolated conductor circuit pattern 21 are very fine in size, it ispreferable to select a photosensitive material for forming the firstprotect layer 33, so as to be able to form the fine portions 24 forforming the deposit coats by means of a photographic printing.

Next, as shown in FIGS. 4(c) and 5(c), an electrically conducting layer35 is formed on the surface of the first protect layer 33 and of thepower supply terminal 32, so as to coat the portions 31 of the circuitpattern 21 for its connection to the power source and as to conductbetween the power source connecting portions 31 and the power supplyterminal 32, while exposing the deposit-coat forming portions 24. It isimportant that the electrically conducting layer 35 will not be formedon portions of the wiring circuit board 22 on the exposed insulatinglayer of the wiring circuit board 22.

Further, the electrically conducting layer 35 may be formed to cover theentire surface of the power supply terminal 32 or to cover only part ofthe terminal. Since the electrically conducting layer 35 is to beemployed as a power supply layer during the electroplating at the laterstep, it is preferable that the electrically conducting layer 35 isformed to conduct between the power source connecting portions 31 andthe power supply terminal 32 through as much wider course as possiblefor ready power supply and for uniform distribution of current densitywithin the surface of the wiring circuit board 22, so that the thicknessof the deposit coat will be more uniform.

This electrically conducting layer 35 is formed with a material which iselectrically conducting and is peelable with heat, solvent or alkali,and the material for forming this layer 35 may be one of, for example,mixtures of an electrically conducting filler with a resin which forminga hardened substance peelable with heat, a resin forming a hardenedsubstance peelable with a solvent or a resin forming a hardenedsubstance peelable with alkali.

For the process for forming the electrically conducting layer 35, suchones may be enumerated as a forming process in which a liquid pasteprepared by mixing a resin which forms a hardened substance madepeelable by heat, solvent or alkali with an electrically conductivefiller is applied through the screen printing process and thereafterhardened, a forming process in which a photosensitive, electricallyconducting film formed by a mixture of the resin which forms thehardened substance made peelable by heat, solvent or alkali with theelectrically conductive filler is thermocompression-bonded,predetermined portions of the bonded film are exposed to light to hardenthe portions, and other portions not exposed to light are then removed,and the like processes. An employment of the process in which theelectrically conducting paste is applied and thereafter hardened ispreferable in view of its excellence in the productivity.

When the resin contained in the electrically conductive paste is aphenolic resin that forms the hardened substance peelable with alkali,it is possible to prevent such problem as a deterioration in thehandling properties from occurring when heated, and the hardenedsubstance can be readily made peelable by immersing it in an alkalinesolution of caustic soda or the like of a relatively low concentration,without requiring any chlorine solvent which is a hazardous material,and is preferable.

In an event when the electrically conductive paste prepared by mixing aphenolic resin that forms the hardened substance made peelable by alkaliwith the electrically conducting filler, it is preferable to form theelectrically conducting layer 35 by heating the applied paste at 50° C.to 150° C. to have it hardened. In the case when the heating temperatureis higher than 150° C., the hardening advances excessively, and thepeeling off with an alkali solution at the subsequent peeling step ofthe electrically conducting layer 35 becomes difficult. When the heatingtemperature is lower than 50° C., on the other hand, there arises noproblem in the peeling ability but the hardening may become insufficientin some occasion, and there arises a possibility that the requiredelectric conductivity cannot be secured upon the electroplating.

For the electrically conducting filler, while not specifically limited,the use of powder of such metal as copper, silver or the like rendersthe electric conductivity of the electrically conducting layer 35 to beeasily secured and is thus preferable. The use of carbon powder as theelectrically conducting filler is preferable in reducing costs for thematerials of the electrically conducting layer 35.

Further, as the electrically conducting layer 35 is formed on thesurfaces of the first protect layer 33 and power supply terminal 32, itis made difficult for the electrically conducting layer 35 to directlycontact with insulating portions on the surface of the wiring circuitboard 22 where any conductor circuit is not formed, and anycontamination or the like damage of the insulating portions due to thepresence of the electrically conducting filler or the like for formingthe electrically conducting layer 35 less occurs.

Next, as shown in FIGS. 4(d) and 5(d), a second protect layer 37consisting of a material electrically insulating and peelable with heat,solvent or alkali is formed to coat the whole surface of theelectrically conducting layer 35 including the portions formed on thefirst protect layer 33 and on the power source connecting portions 31but to expose the portions 24 for forming the deposit coat.

So long as the object of the present invention is not hindered, it doesnot matter if the electrically conducting layer 35 at the portionsformed on the first protect layer 33 and power source connectingportions 31 is exposed to some extent. Further, the electricallyconducting layer 35 formed on the surface of the power supply terminal32 may even be coated with the second protect layer 37 or be exposedwithout being coated.

The second protect layer 37 is formed with a material that does nothinder the subsequent electroplating and peelable with heat, solvent oralkali. For the material of this second protect layer 37, it is possibleto employ, for example, any one alone of the resin that forms thehardened substance peelable with heat, resin that forms the hardenedsubstance peelable with the solvent, and resin that forms the hardenedsubstance peelable with alkali, or a mixture of such insulating filleras glass powder with any of these resins.

For the process of forming this second protect layer 37, further, theremay be enumerated such ones as a process in which an electricallyinsulating paste in liquid type of the resin alone that forms thehardened substance peelable with heat, solvent or alkali or a mixture ofsuch resin with the insulating filler is applied by means of the screenprinting process or the like and is then hardened to form the layer 37;a process in which a photosensitive, electrically insulating film of theresin that forms the hardened substance peelable with heat, solvent oralkali is compression-bonded, predetermined portions of the bonded filmare exposed to light to have them hardened, and other portions notexposed to light are removed, so as to form the layer 37. The use of theprocess in which the electrically insulating paste is applied and thenhardened is preferable in view of its excellence in the productivity.

Further, when the resin contained in the electrically insulating pasteis the phenolic resin that forms the hardened substance peelable withalkali, the hardened substance of the resin can be easily peeled off byimmersing it in an alkaline solution of caustic soda at a relatively lowconcentration, without using any heat or hazardous chlorine solvent, andthis resin is preferable. When this electrically insulating pastecontaining the phenolic resin which forms the hardened substancepeelable with alkali, it is preferable to harden the paste by heating itat 50° C. to 150° C. after the application. When the heating temperatureis higher than 150° C., the hardening advances excessively, so that thepeeling of the second protect layer 37 with the alkaline solution at thelater step of peeling the layer off will be difficult. When the heatingtemperature is lower than 50° C., it does not matter for the peelingability but the hardening may become insufficient, and there may happenthat the characteristics as the protect layer upon performing theelectroplating cannot be shown.

Next, an electric power is supplied to the power supply terminal 32 inthe state where the entire board is immersed in an electroplating bath(not shown), and the deposit coats 27 are formed at the portions 24 forforming the deposit coat, as shown in FIGS. 4(e) and 5(d).

At this time, as the whole surface of the electrically conducting layer35 at the portions formed on the first protect layer 33 and on the powersource connecting portions 31 are coated by the second protect layer 37,the plated metal is prevented from being deposited on other unnecessaryportions than the deposit-coat forming portions 24, and the deposit coat27 excellent in the uniformity of thickness is formed at the formingportions 24. When the second protect layer 37 is not formed on theelectrically conducting layer 35 or when the second protect layer 37 isdefective in the coating, a deposit coat is also formed on the surfaceof the electrically conducting layer 35 exposed upon the electroplating,a desired current density cannot be obtained at some part on thedeposit-coat forming portions 24, and a fluctuation in the thickness ofthe deposit coat 27 formed on the portions 24 becomes remarkable.

Then, the second protect layer 37 and electrically conducting layer 35are peeled off, whereby the isolated conductor circuit pattern 21 asshown in FIGS. 4(f) and 6(b) or the isolated conductor circuit pattern21 hardly damaged at the insulating part and having the deposit coats 27formed to be excellent in the thickness uniformity can be obtained.

In the event when the second protect layer 37 and electricallyconducting layer 35 are peeled off but the first protect layer 33 isleft, the first protect layer 33 can be utilized as a permanent resistof soldering resist or the like. When the permanent resist is notrequired, it will be possible to select a material which can be peeledoff with any of the heat, solvent and alkali as the material for formingthe first protect layer 33, and to peel off also the first protect layer33 together with the second protect layer 37 and electrically conductivelayer 35. This state in which the first protect layer 33 is peeled offis shown in FIGS. 7 and 8.

According to another embodiment attempting the uniformity of the depositcoat in the present invention, there is provided a process in which awiring circuit board 22 provided on the surface only with the isolatedconductor circuit pattern 21 at the initial stage as shown in FIGS. 9and 10, in contrast to the foregoing embodiment of FIGS. 4 to 8. For asubstrate used as the material for the wiring circuit board 22, or amaterial for forming the isolated conductor circuit pattern 21, theremay be enumerated the same one as that in the plating process for theisolated conductor circuit of the foregoing embodiment of FIGS. 4 to 8.

Next, as shown in FIGS. 9(b) and 10(b), the first protect layer 33electrically insulative is formed on the wiring circuit board 22, so asto coat the whole surface of the isolated conductor circuit pattern 21except the deposit-coat forming portions 24 and power source connectingportions 31, and to expand from the part of the surface of the coatedisolated conductor circuit pattern 21 to the position 33A where a powersupply terminal is to be formed and separated from the isolatedconductor circuit pattern 21.

The material for forming this first protect layer 33 or the process forforming the same may be the same as the plating process for the isolatedconductor circuit in the embodiment of FIGS. 4 to 8. The position 33A atwhich the power supply terminal is to be formed is the position wherethe electrically conducting layer is formed at a subsequent step to be apower supply terminal part of the electrically conducting layer, and, asthe power supply terminal part is used as a terminal for supplying thepower as connected to the power source at the subsequent electroplatingstep, its provision at the end edge portions of the wiring circuit board22 as far as possible renders the connection to the power source to beeasier and is preferable.

Next, as shown in FIGS. 9(c) and 10(c), the electrically conductinglayer 35 consisting of the material electrically conducting and peelablewith any of heat, solvent and alkali is formed on the surface of thefirst protect layer 33, so as to coat the position 33A where the powersource connecting portion 31 and power supply terminal are to be formedand to conduct between the power source connecting portion 31 and theposition 33A for forming the power supply terminal while exposing thedeposit coat forming portion 24, and the electrically conducting layer35 having the power supply terminal 35a is formed.

Materials for forming this electrically conducting layer 35 and theprocess for forming the same may also be the same as those in theplating process for the isolated conductor circuit in the foregoingembodiment of FIGS. 4 to 8.

Since the electrically conducting layer 35 is used as the powersupplying layer at the subsequent electroplating step, it is preferablethat, in order to render the thickness of the deposit coat as depositedto be uniform, the layer 35 is formed so that the power sourceconnecting portion 31 and the power supply terminal portion 35a areconducted through as much wider course as possible, for easier powersupply and uniform distribution of current density within the surface ofthe wiring circuit board 22.

Because the electrically conducting layer 35 is formed on the surface ofthe first protect layer 33, the layer 35 is made hard to directlycontact the insulating portions of the wiring circuit board 22 where anyconductor circuit or the like is not formed, so that the insulatingportions are less damaged to be contaminated due to the presence of theelectrically conducting filler or the like for forming the electricallyconducting layer 35.

Next, as shown in FIGS. 9(d) and 10(d), the second protect layer 37consisting of the material electrically insulating and peelable withheat, solvent or alkali is formed to coat the whole surface of theelectrically conducting layer 35 except the power supply terminalportion 35a in the surface of the first protect layer 33. The materialsfor forming this second protect layer 37 and its forming process mayalso be the same as those in the plating process for the isolatedconductor circuit in FIGS. 4 to 8.

Next, in a state of being immersed in the electroplating solution (notshown), a power is supplied to the power supply terminal portion 35a ofthe electrically conducting layer 35, and the deposit coat 27 is formedat the deposit-coat forming portion 24 of the isolated conductor circuitpattern 21, as shown in FIGS. 9(e) and 11(a).

Since at this time the whole surface of the conducting layer 35 exceptthe power supply terminal portion 35a is coated by the second protectlayer 37, any plated metal deposition on unnecessary portions other thanthe deposit-coat forming portion 24 can be prevented, and the depositcoat 27 excellent in the thickness uniformity can be formed at thedeposit-coat forming portion 24. In an event when the second protectlayer 37 is not formed on the surface of the conducting layer 35 or whenthe second protect layer 37 is defective in its coating, the depositcoat is formed also on the surface of the layer 35 exposed upon theelectroplating, there arises a part where the desired current densitycannot be obtained on the deposit-coat forming portion 24, and thethickness of the deposit coat 27 formed on the portion 24 is remarkablyfluctuated.

Next, the second protect layer 37 and conducting layer 35 are peeledoff, whereby such isolated conductor circuit pattern 21 as shown inFIGS. 9(b) and 11(b) or the isolated conductor circuit pattern 31 hardto be damaged at the insulating portion and having the deposit coat 27excellent in the thickness uniformity can be obtained.

When the second protect layer 37 and conducting layer 35 are peeled offbut the first protect layer 33 is kept remain, the first protect layer33 can be utilized as such permanent resist as a soldering resist. Whensuch permanent resist is not required, on the other hand, a materialmade peelable with any of heat, solvent and alkali is selected as theone for forming the first protect layer 33, so that the first protectlayer 33 can be also peeled off together with the second protect layer37 and conducting layer 35. This state where the first protect layer 33is also peeled off is shown in FIGS. 12 and 13.

In the followings, experiments of the plating process for the isolatedconductor circuit to which the present invention relates as shown inFIGS. 4 to 13 shall be described in further detail.

EXPERIMENT 6:

First, a ceramic series wiring circuit board 22 having on the surfacethe isolated conductor circuit pattern 21 in which copper was coatedwith nickel while nickel was coated by gold and the copper-made powersupply terminal 32 formed as separated from the circuit pattern 21 wasprepared, and the steps shown in FIG. 4 were sequentially performed. Inthis case, the power supply terminal was positioned at an end edgeportion of the wiring circuit board.

At this time, as shown in FIG. 4(b), the isolated conductor circuitpattern 21 was coated on the whole surface except the deposit-coatforming portions 24 (minimum size 150×150 μm) and the power sourceconnecting portions 31, and the electrically insulating first protectlayer 33 expanding from the surface of the coated circuit pattern 21 tothe power supply terminal 32 was formed on the wiring circuit board 22.This first protect layer 33 was formed by providing its pattern by meansof the screen printing process with a liquid resin paste for use as thesoldering resist (permanent resist) employed, and heat-treating thispattern at 150° C. for 60 minutes.

Next, as shown in FIG. 5(c), the electrically conducting layer 35consisting of a material peelable with alkali was formed on the firstprotect layer 33 through a pattern printing by means of the screenprinting process with an electrically conducting paste (commodity name"Silver Paste LS-520" manufactured by Kabushiki Kaisha Asahi KagakuKenkyusho) containing silver powder as the electrically conductingfiller and a phenolic resin that forming the hardened substance peelablewith alkali as the resin, and a heat treatment of this pattern at 80° C.for 30 minutes. This electrically conducting layer 35 was formed on thesurfaces of the first protect layer 33 and of the power supply terminal32, so as to coat the power source connecting portion 31 on the isolatedconductor circuit pattern 21 and to conduct between the power sourceconnecting portions 31 and the power supply terminal 32, while exposingthe deposit-coat forming portions 24.

Then, as shown in FIG. 4(d), the second protect layer 37 consisting of amaterial peelable with alkali was formed so as to coat the wholesurfaces at portions of the conducting layer 35 on the first protectlayer 33 and on the power source connecting portions 31, while exposingthe deposit-coat forming portions 24.

In forming this second protect layer 37, its pattern was printed bymeans of the screen printing process with an electrically insulatingpaste (commodity name "Plating Resist MR300CNo6" manufactured by K.K.Asahi Kagaku Kenkyusho) containing a phenolic resin which forming thehardened substance peelable with alkali and electrically insulating, andthis pattern was heat treated at 80° C. for 30 minutes.

Next, an electroplating of tin was performed with respect to thedeposit-coat forming portions 24 in the isolated conductor circuitpattern 21 as shown in FIG. 4(e), by immersing the entire board in anelectroplating solution of tin and thereafter supplying a power to theterminal 32, and the deposit coats 27 consisting of tin were formed. Atthis time, the electroplating was performed under conditions suitablefor obtaining a thickness of 5 μm for the deposit coat.

Then the thus obtained board was immersed in caustic soda solution (4%),the second protect layer 37 and conducting layer 35 were peeled off bymeans of an ultrasonic cleaning system of applying an ultrasonic wave tothe board being immersed, and such wiring circuit board 22 as shown inFIG. 4(f) in which the deposit was performed with respect to theisolated conductor circuit pattern 21 was obtained.

EXPERIMENT 7:

First, a ceramic series wiring circuit board 22 having on the surfacethe isolated conductor circuit pattern 21 including a nickel coating oncopper and a further gold coating thereon was prepared, and such stepsas shown in FIG. 9 were sequentially performed.

As shown in FIG. 9(b), the first protect layer 33 electricallyinsulating was formed on the wiring circuit board 22, so as to coat thewhole surface of the isolated conductor circuit pattern 21 except thedeposit-coat forming portion 24 (minimum size 150×150 μm) and the powersource connecting portion 31, and to expand from the coated surface partof the isolated conductor circuit pattern 21 to the position 33A wherethe power supply terminal is to be formed.

At this time, the position 33A for forming the power supply terminal wasseparated from the isolated conductor circuit pattern 21 and waspositioned at the end edge part of the wiring circuit board 22. Further,the first protect layer 33 was formed by forming its pattern through thescreen printing process with the soldering resist (permanent resist) useliquid resin paste employed, and heat-processing this pattern at 150° C.for 60 minutes.

Then, the electrically conducting layer 35 consisting of the materialpeelable with alkali and having the power supply terminal portion 35awas formed on the first protect layer 33 as shown in FIG. 9(c),employing the same electrically insulating paste and in the same manneras those employed in Experiment 6. This conducting layer 35 was formedon the first protect layer 33, so as to coat the power source connectingportion 31 and the position 33A for forming the power supply terminal,and to conduct between the connecting portion 31 and the terminalforming position 33A, while exposing the deposit-coat forming portion24.

Next, the second protect layer 37 consisting of the material peelablewith alkali was formed with the same electrically insulating paste andin the same manner as in Experiment 6 and as shown in FIG. 9(d), so asto coat the whole surface of the conducting layer 35 except the powersupply terminal portion 35a, while exposing the deposit-coat formingportion 24.

Then, after immersing in the same electroplating solution of tin as thatemployed in Experiment 6, the power was supplied to the power supplyterminal portion 35a of the conducting layer 35 to perform theelectroplating of tin on the deposit-coat forming portion 24 in theisolated conductor circuit pattern 21 and the deposit coat formingportion 24 of tin was formed. For performing the electroplating at thistime, conditions for rendering the thickness of the deposit coat to be 5μm were set.

Then, the second protect layer 37 and conducting layer 35 were peeledoff with the ultrasonic wave cleaning system by applying the ultrasonicwave to the board in the state of immersing the thus obtained boardwithin the caustic soda solution (4%), and such wiring circuit board 22as shown in FIG. 9(f) in which the plating was performed with respect tothe isolated conductor circuit pattern 21 was obtained.

EXPERIMENT 8:

In the same manner as in Experiment 7 except that the heat treatmentconditions with respect to the electrically conducting paste for formingthe conducting layer 35 were made to be 50° C. for 30 minutes, thewiring circuit board 22 in which the plating was performed with respectto the isolated conductor circuit pattern 21 was obtained.

EXPERIMENT 9:

In the same manner as in Experiment 7 except that the heat treatmentconditions with respect to the electrically conducting paste for formingthe conducting layer 35 were made to be 150° C. for 30 minutes, thewiring circuit board 22 in which the plating was performed with respectto the isolated conductor circuit pattern 21 was obtained.

EXPERIMENT 10:

In the same manner as in Experiment 7 except that the heat treatmentconditions with respect to the electrically conducting paste for formingthe conducting layer 35 were made to be 170° C. for 30 minutes, thewiring circuit board 22 in which the plating was performed with respectto the isolated conductor circuit pattern 21 was obtained.

EXPERIMENT 11:

In the same manner as in Experiment 7 except that the minimum size ofthe deposit-coat forming portion 24 on the isolated conductor circuitpattern 21 was made to be 50×50 μm, a photosensitive dry film(plating-resisting) was used as the material for forming the firstprotect layer 33, and the formation of the first protect layer 33 wasperformed in a photographic printing, the wiring circuit board 22 inwhich the plating was performed with respect to the isolated conductorcircuit pattern 21 was obtained.

EXPERIMENT 12:

In the same manner as in Experiment 7 except that the minimum size ofthe desposit-coat forming portion 24 on the isolated conductor circuitpattern 21 was made to be 50×50 μm, a photosensitive dry film(plating-resisting) forming the substance peelable with alkali was usedas the material for forming the first protect layer 33, the firstprotect layer 33 was formed in the photographic printing, and the firstprotect layer 33 was peeled off simultaneously with the peeling off ofthe second protect layer 37 and conductive layer 35, the wiring circuitboard 22 in which the plating was performed with respect to the isolatedconductor circuit pattern 21 was obtained.

EXPERIMENT 13:

In the same manner as in Experiment 7 except that the second protectlayer 37 was formed by using an electrically conducting paste formingthe hardened substance peelable with heat as the material for formingthe layer 37 (commodity name "Strip Mask #503B-SH" by K.K. Asahi KagakuKenkyusho; hardening conditions: 120° C., hardening time 15 minutes;peeling conditions: peeling temperature 180° C., treating time 15minutes), printing the pattern through the screen printing process, andheat-treating this pattern at 120° C. for 15 minutes; that theelectrically conducting layer 35 was formed by employing as its formingmaterial a mixture of the electrically conducting paste peelable asheated with silver powder, printing its pattern through the screenprinting process, and heat-treating the pattern at 120° C. for 15minutes; and that the peeling off of the second protect layer 37 andconducting layer 35 was performed through a heat treatment at 180° C.for 15 minutes; the wiring circuit board 22 in which the plating wasperformed with respect to the isolated conductor circuit pattern 21 wasobtained.

The wiring circuit board 22 obtained through the respective Experimentswere evaluated as to the appearance of the isolated conductor circuitpattern 21 and insulating portions and the thickness of the depositcoat. For the appearance of the isolated conductor circuit, whether ornot the isolated conductor circuit pattern 21 was damaged by anyside-etching was evaluated through visual observation, and a case notdamaged was denoted by G.

For the appearance of the insulating portion, the evaluation through thevisual observation was made whether or not the insulating portion wasdamaged to be contaminated by the electrically conducting fillercontained in the electrically conducting layer 35 and caused to remainon the surface of the insulating portion where the isolated conductorcircuit pattern 21 or the like was not formed on the surface of thewiring circuit board 22, and whether or not the insulating portion wasdamaged by the conducting layer 35 caused to remain on the insulatingportion together with the first protect layer 33 without being peeledoff, and the case not damaged was marked as G, while a case partlydamaged was marked N.

For the thickness of the deposit coat, the thickness of the deposit coatconsisting of tin as formed on the surface of the isolated conductorcircuit pattern 21 was measured at 10 positions through observation ofsection, and their average value, the largest value, the smallest value,and difference value (R) between the largest and smallest values wereobtained, of which results were as shown in a following Table.

While it is not always that the foregoing embodiments of FIGS. 4 to 13are excellent in all properties as compared with the embodiment of FIGS.1 to 3, it is considered possible in general to improve the propertiesof the embodiment of FIGS. 1 to 3.

                                      TABLE                                       __________________________________________________________________________    Experiment                                                                              6   7   8   9   10  11  12  13                                      __________________________________________________________________________    Electrically                                                                            alkali                                                                            "   "   "   "   "   "   heat                                    Conduct'g Paste                                                                         peeling                     peeling                                 Electrically                                                                            alkali                                                                            "   "   "   "   "   "   heat                                    Insulat'g Paste                                                                         peeling                     peeling                                 Heat'g Conditions                                                                       80° C.                                                                     80° C.                                                                     50° C.                                                                     150° C.                                                                    170° C.                                                                    80° C.                                                                     80° C.                                                                     80° C.                           for Elec. Cond.                                                                         30 m.                                                                             30 m.                                                                             30 m.                                                                             30 m.                                                                             30 m.                                                                             30 m.                                                                             30 m.                                                                             30 m.                                   Paste                                                                         Appear. of Isolt'd                                                                      G   G   G   G   G   G   G   G                                       Cond. Circuit                                                                 Appear. of                                                                              G   G   G   G   N   G   G   G                                       Insulat'g Portion                                                             Thickness of Deposit                                                          Coat (μm)                                                                  Av.       5.06                                                                              5.05                                                                              5.01                                                                              5.05                                                                              5.07                                                                              4.98                                                                              5.05                                                                              5.07                                    Lgst.     5.12                                                                              5.11                                                                              5.10                                                                              5.12                                                                              5.13                                                                              5.02                                                                              5.15                                                                              5.13                                    Smst.     4.98                                                                              4.98                                                                              4.88                                                                              4.98                                                                              4.99                                                                              4.87                                                                              4.99                                                                              4.99                                    R         0.14                                                                              0.13                                                                              0.22                                                                              0.14                                                                              0.14                                                                              0.15                                                                              0.16                                                                              0.14                                    Judg.     G   G   G   G   G   G   G   G                                       __________________________________________________________________________

Further, according to another feature of the present invention, therecan be provided a process of plating on the isolated conductor circuitallows for formation of a deposit coat excellent not only in theuniformity of thickness but also in the deposition characteristic bymeans of the electroplating at desired portions on the isolatedconductor circuit formed on the wiring circuit board, without damagingto the isolated conductor circuit formed on the surface of the wiringcircuit board or to insulating portions where no isolated conductorcircuit is formed any damage.

Referring to FIGS. 14 and 15, the arrangement in which the wiringcircuit board 22 provided on the surface with the isolated conductorcircuit pattern 21 and the power supply terminal 32 formed as separatedfrom the pattern 21 is also employed in the present embodiment, to besubstantially the same as the foregoing embodiments.

In the present embodiment, on the other hand, the first protect layer 33electrically insulating is formed on the wiring circuit board 22together with a projected part 33a formed between the deposit coatforming portions 24 and the power source connecting portions 31, incontract to the first protect layer 33 formed at the portion where theelectrically conducting layer 35 or the second protect layer 37 is to beformed at a subsequent step.

Here, the projected part 33a acts to prevent the deposit coat formingportions 24 from being filled with the electrically conducting paste orthe like for forming the conducting layer 35 or second protect layer 37at the later step, when the paste is caused to expand towards thedeposit coat forming portions 24. Its projecting amount is properlyadjusted in accordance with the electric conductivity, formed thicknessof the second protect layer, or the distance between the projected part33a and so on.

For the shape of the projected part 33a, the same is formed in a wavyshape in plan view, between the deposit coat forming portions 24 and thepower source connecting portions 31 in the embodiment shown here, but isnot required to be specifically limited so long as the same is formed ina shape effective to prevent the deposit-coat forming portions 24 frombeing filled with the electrically conducting paste or the like. Theprojected part 33a formed closer to the deposit-coat forming portions 24can reliably prevent the portions 24 from being filled and ispreferable.

For a process for forming the projected part 33a, one in which theprojected part 33a is formed at a plurality of steps such that the firstprotect layer 33 of the same thickness all over a part where the firstprotect layer is to be formed, and thereafter a projecting part only ofthe projected part 33a is formed by supplying again the resin paste orthe like, will be general, but it is also possible to form the projectedpart at one time.

Now, as shown in FIGS. 14 to 16, the deposit coat can be formedsubstantially in the same manner as in the foregoing case of FIGS. 4 to6.

Since at this time the projected part 33a is formed between thedeposit-coat forming portions 24 and the power source connectingportions 31, any risk in which the electrically conducting paste or thelike supplied to coat the connecting portions 31 expands over to thedeposit-coat forming portions 24 can be effectively prevented fromoccurring.

The deposit coat 27 can be reliably formed at their forming portions 24,and it is enabled to effectively form the deposit coat 27 excellent inthe deposition characteristic.

As shown in FIGS. 17 and 18, on the other hand, the first protect layer33 can be utilized as such permanent resist as the soldering resist inthe case where the second protect layer 37 and conducting layer 35 arepeeled off but the first protect layer 33 is kept remain, whereas, inthe case when the permanent resist is not required, a material peelablewith any one of heat, solvent and alkali is selected as the material forforming the first protect layer 33 so that the first protect layer 33will be also peeled off together with the second protect layer 37 andconducting layer 35.

Further, another embodiment of the present invention excellent in thedeposition characteristic as a result of the electroplating is shown inFIGS. 19 to 21, in which a process employing a wiring circuit board 22having only the isolated conductor circuit pattern 21 formed at theinitial stage is employed in contrast to the foregoing embodiment ofFIGS. 14 to 18. In this case, it is preferable that the projected part33a is formed to be close to the deposit coat forming portions 24 and tobe annular in plan view in the embodiment shown, while the shape may beany one which can attain the desired object and needs not bespecifically limited.

As also shown in FIGS. 22 and 23, an arrangement in which the firstprotect layer 33 is peeled off together with the second protect layer 37and conducting layer 35 likewise the case of FIGS. 7 and 8 may also beemployed.

The foregoing arrangements of FIGS. 14 to 18 as well as FIGS. 19 to 23are the same as those of FIGS. 4 to 8 and FIGS. 9 to 13, the sameconstituent elements as those in FIGS. 4 to 8 and FIGS. 9 to 13 areshown with the same reference numbers in FIGS. 14 to 18 and FIGS. 19 to23, and the same function and effect can be attained.

In still another embodiment shown in FIG. 24, the wiring circuit board22 provided on the surface with the isolated conductor circuit pattern21 and with the power supply terminal 32 formed as separated from thecircuit pattern 21 is further provided with a projection 33b formedbetween the circuit pattern 21 and the terminal 32 and to have a recessin top face, whereby the same function as the projected part 33a ofFIGS. 14 to 18 can be realized by this projection 33b.

In another embodiment shown in FIG. 25, the projection 33b having therecess in the top face is formed to be annular in the plan view, on thewiring circuit board 22 carrying only the isolated conductor circuitpattern 21 formed at the initial stage, whereby the same function as theprojected part 33a of FIGS. 19 to 23 can be realized.

All other aspects of the foregoing arrangements of FIGS. 24 and 25 arethe same as those in FIGS. 4 to 8 and 14 to 18 and FIGS. 9 to 13 and 19to 23, and the same constituent elements are shown in FIGS. 24 and 25with the same reference numbers as those in the foregoing embodiments.

What is claimed is:
 1. A process of plating on isolated conductorcircuit pattern wherein a deposit is formed through an electroplating onan isolated conductor circuit pattern of wiring circuit board,characterized in comprising the steps of forming on the wiring circuitboard an electrically conducting layer consisting of a materialelectrically conducting and peelable with one of heat, solvent andalkali, so as to be at least in contact with the isolated conductorcircuit pattern on which a deposit coat is to be formed; forming apeelable protect layer on at least a portion of the electricallyconducting layer other than a portion on which the deposit coat is to beformed and to be superposed on the electrically conducting layer;causing a metal to deposit on a portion not coated by the protect layerthrough an electroplating performed with the electrically conductinglayer used as a power supply layer; and peeling off the electricallyconducting layer and the protect layer left on the wiring circuit board.2. The process according to claim 1 wherein the protect layer isphotosensitive, said photosensitive protect layer being formed at theportion where the deposit coat is to be formed and removed through anexposure to light and development.
 3. The process according to claim 1wherein the electrically conducting layer is of a photosensitivematerial.
 4. The process according to claim 1 wherein the electricallyconducting layer contains an electrically conducting filler.
 5. Theprocess according to claim 4 wherein the electrically conducting filleris at least one selected from the group consisting of carbon, copper andsilver.
 6. A process of plating on isolated conductor circuit patternformed on a wiring circuit board to form a deposit coat through anelectroplating, characterized in comprising the steps of:(a) forming anelectrically insulating first protect layer on the wiring circuit board,to coat the whole surface of the isolated conductor circuit patternexcept a deposit-coat forming portion and a power source connectingportion, and to reach a portion of the surface of the board to whichportion a power is to be supplied; (b) forming an electricallyconducting layer consisting of an electrically conducting material andpeelable with one of heat, solvent and alkali on the surfaces of thefirst protect layer and of the portion to which the power is to besupplied, to coat the power source connecting portion and the portion towhich the power is to be supplied and to conduct between the powersource connecting portion and the portion to which the power is to besupplied while exposing the deposit-coat forming portion; (c) forming asecond protect layer consisting of a material electrically insulatingand peelable with one of heat, solvent and alkali, to coat the wholesurfaces of portions of the electrically conducting layer formed on thefirst protect layer and on the power source connecting portion whileexposing the deposit-coat forming portion; (d) forming a deposit coat atthe deposit-coat forming portion on the isolated conductor circuitpattern through an electroplating performed with a power supplied to theportion to which the power is to be supplied; and (e) peeling off thesecond protect layer and electrically conducting layer.
 7. The processaccording to claim 6 wherein the step (a) includes a step of formingpreliminarily the power supply terminal by separating the electricallyinsulating first protect layer from the isolated conductor circuitpattern, and the step (b) includes a step of coating the power sourceconnecting portion and the preliminarily formed power supply terminaland conducting between them with a peelable material layer.
 8. Theprocess according to claim 6 wherein a photosensitive material is usedas the material for forming the first protect layer.
 9. The processaccording to claim 6 wherein a material which forms a substance peelablewith one of heat, solvent and alkali is used as the material for formingthe first protect layer.
 10. The process according to claim 6 wherein,at the step (b), the electrically conducting layer is formed by applyingan electrically conducting paste prepared by mixing an electricallyconducting filler with a resin and hardening the applied paste.
 11. Theprocess according to claim 10 wherein a phenolic resin that forms ahardened substance peelable with alkali is used as the resin containedin the electrically conducting paste.
 12. The process according to claim10 wherein at least one selected from the group consisting of carbonpowder, copper powder and silver powder is employed as the electricallyconducting filler contained in the electrically conducting paste. 13.The process according to claim 6 wherein, at the step (c), the secondprotect layer is formed by applying an electrically insulating pastecontaining a resin, and hardening the applied paste.
 14. The processaccording to claim 13 wherein a phenolic resin that forms a hardenedsubstance peelable with alkali is used as the resin contained in theelectrically insulating paste.
 15. The process according to claim 6wherein the step (a) includes a step of forming a projected part betweenthe deposit-coat forming portion and the power source connectingportion, while forming the first protect layer.
 16. The processaccording to claim 15 wherein the step (a) includes a step of forming aprojected part so as to encircle the deposit-coat forming portion. 17.The process according to claim 6 wherein the step (a) includes a step offorming a recess between the deposit-coat forming portion and the powersource connecting portion, while forming the first protect layer. 18.The process according to claim 17 wherein the step (a) includes a stepof forming a recess so as to encircle the deposit-coat forming portion.